With a bit of tweaking, perhaps writing a custom component or two I am
pretty sure you could generate a testbench in Virtual Breadboard.

It depends if the PICs you are using are supported, and what your timeframe
is

Virtual Breadboard V1.1 !New Version supports
PIC16F877,F8X,16C71X,16C5X,12C5XX

You may need to write a "Emulator" for your VHDL tester as a custom VBB
component as a starter though. If the VHDL is just for testing then the
Emulator may get you most of the way.

If only VHDL will do then I do have a prototype VHDL compoenent, its pretty
young and fairly limited but I would be interested in working with someone
who would be using it in a real-world situation.

Regards,
James Caska
caska@virtualbreadboard.com
ujVM - 'The worlds smallest java virtual machine'




-----Original Message-----
From: pic microcontroller discussion list
[mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Mik Juneau Kim
Sent: Sunday, 4 November 2001 8:53 AM
To: PICLIST@MITVMA.MIT.EDU
Subject: [EE]: VHDL testbenches


Hi!
I'm doing a project that involves multiple devices (PIC is one) on a bus and
PLD to arbitrate them. The design is fairly complex. My problem is how best
to generate test bench in VHDL.

Currently, I am using paper to generate the timing diagram, then coding that
into VHDL code. Under multiple clocks used by all these devices, this gets
very messy. I tried HDLBencher, but that is hopelessly inadequate for
multiple clock sources.

I would like to hear about how some of you are generating test benches for
your designs.

Thanks.

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