On Fri, 2 Nov 2001, Lawrence Lile wrote:

> I've been working on a two-byte version of the RAMless delay loop, which
> uses FSR to store the high byte.  In assembler I can get it to work fine.
> In CCS C, there seems to be a problem in simulation under MPLAB, because a
> skpz instruction clearly always skips, regardless of the state of the
> status,Z bit on the adjacent watch window+ACE-  (aargh) Simulation works OK in
> Hitech C under MPLAB.    SO far, both versions have a fixed delay (which is
> what I happen to need for a project I am working on today+ACE-)
>
> //     ASSEMBLER VERSION
> +ADsAOw- loop 10,000 cycles +AD0- 10,000 / 5.0351 +AD0- 1986  loops
> +ADsAOw- +AD0- 0x7C2  loops  FSR needs to be 0x07+-1for it to work right
> MAINLOOP
>  movlw -(0x07+-1)
>  movwf FSR
>  movlw -(0xC2+-1)
>
> Delay500Loop
>  subwf       PCL,W
>  subwf       PCL,W
>  skpz
>  goto      Delay500Loop
>  movf FSR,w
>  subwf       PCL,W
>  subwf       PCL,W
>  movwf FSR
>  skpnz
>  goto endofloop


Why not just use

   decf  fsr,f  ;
   skpnz
    goto   endofloop


>  clrw
>  goto Delay500Loop
> endofloop:
>     nop


Also, is this for a 12bit core or 14bit core? If you're using the 14-bit
core then a simpler "addlw -1" would suffice.

Scott

PS. Nikolai tells me he has some nifty variations on Dwayne's trick.
Unfortunately the list server doesn't like him right now...

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