At 03:18 PM 11/1/01 +0100, K=FCbek Tony wrote:

>Neat ! however..
>
>a bit concerned over 8 bit pcl rollover ( i.e. from 0xFF -> 0x00 )
>lets try with the following:
>Let's try with 1 loop delay and let PCL have the value 0xFF at the
>first subwf.
>
>W =3D 1 -> a 5 cycle delay ( excluding and returns or calls )
>
>Delay500Loop_1                  ; W =3D 1
>      subwf       PCL,W          ; PCL =3D 0xFF ( 255 ) -> F-W =3D 254
>      subwf       PCL,W            ; PCL =3D 0x00 -> F-W =3D 254 !!!=
 gotcha...
>      skpz                       ;
>       goto      Delay500Loop    ; loop forever....

Nope - no gotcha!  W is an 8 bit register.  I simulated with boundary=20
conditions as you describe and there was no problem whatsoever.

It *does* work!  (MPLAB 5.40, tried with both 12c508 & 16f84).

dwayne



Dwayne Reid   <dwayner@planet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax

Celebrating 17 years of Engineering Innovation (1984 - 2001)

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