On Thu, Oct 18, 2001 at 12:13:25PM -0700, Harold M Hallikainen wrote:
>         Keeping the PIC powered but asleep is an interesting approach.

Glad you like it.

> You'd
> then have to generate an interrupt or something to wake it up.  I guess
> you could tie RB0/INT to an unbacked supply. Generate an interrupt on it
> going high, taking the processor out of sleep. In the main loop, if RB0
> is low, go into sleep.

That's the basic idea. The PIC would go to sleep when power isn't applied and
be woken up when power is applied.

>         What about the watchdog timer? I like using a watchdog, but this will
> wake the processor, for a short time, every 2 seconds or so. Even for a
> short time, this probably takes a lot more energy than an unclocked SRAM.

True. But the difference is that a watchdog will only bring the PIC out of
sleep, not reset it. But cranking up the oscillator will suck up some juice.

>         Interesting approach, though. I like it because of the lower parts count
> ("The ideal design has zero parts.")

Essentially there should only be one or two additional parts: the steering
diode for the battery, and possibly a MOSFET switch to remove power from the
other parts of the circuit.

BAJ
>
> Harold
>
>
>
> On Thu, 18 Oct 2001 14:04:01 -0400 Byron A Jeff <byron@CC.GATECH.EDU>
> writes:
> > On Thu, Oct 18, 2001 at 08:25:18AM -0700, Harold M Hallikainen wrote:
> > >         I've generally used a 1F capacitor that is charged through
> > a diode and
> > > current limit resistor from the +5V supply. I then use a
> > Dallas/Maxim
> > > 1210 to handle power switching. You also route the chip select to
> > the RAM
> > > through the 1210 to prevent any reads or writes during power down.
> > Write
> > > are obviously a problem, corrupting RAM. Reads are also  a problem
> > since
> > > the data lines would then attempt to power the powered down PIC,
> > quickly
> > > discharging your battery or capacitor.
> >
> > This discussion seems to be going on in 3 or 4 threads at the same
> > time.
> > I posted the same basic question but got no responses.
> >
> > Here's my question: Why not skip the RAM supervisor, and simply
> > power the
> > PIC along with the RAM? Put the PIC into sleep after it completes a
> > read or
> > write, with the CE held high. Then you have no write corruption, the
> > PIC
> > continues to be powered for the duration, and is only draws
> > microamps in
> > sleep mode.
> >
> > This was my plan. I was concerned about doing a partial power down
> > because
> > I plan to have latches inbetween the RAM and the PIC. But there
> > should be
> > no power draw if all of the inputs/outputs of the latches are
> > tri-stated?
> > Right?
> >
> > The task here is on my short list. Looking forward to some more
> > discussion
> > on the subject.
> >
> > BAJ
> >
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> >
> >
>
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