Peter L. Peres wrote:
>
> Hi,
>
> I made a clock to test a timer routine implemented using Bob Ammermann's
> and Roman Black's idea (of accumulator that is substracted from each TMR0
> overflow), and the clock runs slow, with a fast crystal. The crystal is
> 4MHz +60ppm (measured) and the clock loses about 5 seconds in two hours,
> which is -700ppm or so. I use psc=0 (div 2) which causes interrupts at
> about 1953Hz with 4MHz crystal. The accumulator adds an extra tick every 8
> ticks with this scheme (TMR0: /2/256 = Tcyc/512 etc: 1000000/512 1953.125
> - where the .125 becomes 1 extra after 8 ticks).
>
> Since until now I did all my clocks using interrupt-less PICs using
> constant run time code etc. I need to ask whether there is any known
> problem with the PIC that causes this (it's a 16F84 for development),
> before I take my code apart again. The timer tick is the only used
> interrupt, but all interrupt sources are handled in stubs in the ISR so
> stray pulses are excluded. Scoping pins brings no joy (I do PORTB ^= 0x80;
> at the end of each TMR0 ISR). I am almost sure that I missed something in
> this code but I have to ask...


Peter, I think you may have misunderstood the
system? Why add the extra tick?? The beauty of
the system is that you only need one 24bit number
which is as accurate as timer0 tick.

So, for your example, you have a 4MHz crystal,
1MHz clock, prescaler/2 so timer0 tick is
500,000 to a second (2ppm).

So the system will ALWAYS be accurate to within
2ppm, and since your crystal is only good for
maybe 50ppm at best the software system can't
be a problem. :o)

Have you seen my spuedo code here:
http://centauri.ezy.net.au/~fastvid/one_sec.htm
-Roman

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