(REPOSTED, DUE TO ERROR IN TOPIC FORMAT)

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Thanks to James Newton for informing me about this error.  I am new
to this Mailing List.  Guess you learn as you go...  Dan
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Interested in creating a READY / WAIT State for the 17C765 CPU.

I have a device I am interested in interfacing to the 17C756 Multiplexed

Adr/Data Bus.  It requires the CPU to yield to a READY / WAIT Signal in
data transfers between them.  Mainly during the second half of a I/O
Instruction Execution when it is actively transferring the data byte.

This device usually works with the Z80, 8086 Processors which has Ready
/ Wait Signaling.  It's Timing requirement is such that a VALID ADDRESS
is set before the  /OE or /WE signal occurs.  Once either the /OE or /WE

signal is asserted, the device could signal a /WAIT, (as it might be
busy servicing some other task) telling the CPU a valid I/O DATA
Transfer has to be delayed until it releases the WAIT STATE.

Normally the 17C756 can't be paused during such an I/O transfer on the
bus.  Now I was thinking, if the 17C756 CPU Clock was INHIBITED during
the device  /WAIT signal, it would place the current I/O Instruction
Execution in limbo,  until the device can I/O a valid data transfer.

I know this can be a bit trick, because it depends on just when the WAIT

is asserted in regard to the  (Clock/4) of an I/O instruction execution.

Do you have any idea if this can work.  Would it require a bit more then

just a CLOCK INH Circuit.

Dan Marchesani, WB2ZTK

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