Hi Bob Ammerman

    Thanks for your reply, and your words of assurance that I am
on the right track  Yes it is a bit tricky, and I am considering all
Timing Parameters and Logic very carefully, but until I test it in
hardware who know if I got it all correct.  I guess that is what
design is all about.

Thanks again,
Dan

Bob Ammerman wrote:

> If the timing of the WAIT is right then a clock inhibit should work fine,
> since the PIC is fully static. The logic to get this right might be a bit
> tricky, though.
>
> Bob Ammerman
> RAm Systems
> (contract development of high performance, high function, low-level
> software)
>
> ----- Original Message -----
> From: "Dan & Vijay Marchesani" <danvj@EARTHLINK.NET>
> To: <PICLIST@MITVMA.MIT.EDU>
> Sent: Tuesday, September 25, 2001 8:29 PM
> Subject: Ready /Wait State for the 17C756
>
> > Interested in creating a READY / WAIT State for the 17C765 CPU.
> >
> > I have a device I am interested in interfacing to the 17C756 Multiplexed
> > Adr/Data Bus.  It requires the CPU to yield to a READY / WAIT Signal in
> > data transfers between them.  Mainly during the second half of a I/O
> > Instruction Execution when it is actively transferring the data byte.
> >
> > This device usually works with the Z80, 8086 Processors which has Ready
> > / Wait Signaling.  It's Timing requirement is such that a VALID ADDRESS
> > is set before the  /OE or /WE signal occurs.  Once either the /OE or /WE
> > signal is asserted, the device could signal a /WAIT, (as it might be
> > busy servicing some other task) telling the CPU a valid I/O DATA
> > Transfer has to be delayed until it releases the WAIT STATE.
> >
> >  Normally the 17C756 can't be paused during such an I/O transfer on the
> > bus.  Now I was thinking, if the 17C756 CPU Clock was INHIBITED during
> > the device  /WAIT signal, it would place the current I/O Instruction
> > Execution in limbo,  until the device can I/O a valid data transfer.
> >
> > I know this can be a bit trick, because it depends on just when the WAIT
> > is asserted in regard to the  (Clock/4) of an I/O instruction execution.
> >
> > Do you have any idea if this can work.  Would it require a bit more then
> > just a CLOCK INH Circuit.
> >
> > Dan Marchesani, WB2ZTK
> >
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>
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