You don't need to refresh DRAM while you are reading or writing from/to
it, just make sure your operations visit a whole DRAM page within the
required time (i.e. 128 or 256 or 512 operations in a row within 4 or 8
msec - easy).

A quick and sneaky way out of the pin maze for a fast data sampler is a
FIFO RAM combined with continuous flash A/D like HM1175 and friends or
higher. The FIFO has only write, read, clock, and reset pins beyond the
data path, which is 4 or 8 or 16 bits wide. All you need to do is to
connect the AD clock and the FIFO clock together and supply /WR to the
FIFO with correct phase (every clock cycle). This yields a 40MSPS sampler
(using HM1175 etc). There are other options. The address counter is in the
FIFO and it is reset at the beginning.

The only problem is getting hold of FIFOs. They are used in some high end
network and video cards and some are unbelievably fast. Try to find
something suitable.

Peter

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics