Russell McMahon wrote...
>I will happily
>admit that I do not (yet) know the formal transient performance of "my"
>design...

/Somehow, after going 'round and 'round in circles with you on this
/design for over a week now, this doesn't surprise me a bit.
/Since you've decided- now that we've mentioned it in passing- to do a
/bit of testing re transient response, here are two other things to
/look at while you're at it:

All statements of "fact" below may optionally be prefixed with "IMHO :-) "
if desired.

Someone with a thinner skin than mine might just suspect you were trying to
be rude to me but fortunately my skin is getting thick and wizened. I have
noticed us going in a few circles lately but had the distinct impression
that I was following someone else's footprints at the time :-).

Re transient response - what I referred to was "formal transient
performance". I do not have theoretical numerical predictions of the
response - what I can tell you is how it has performed in practice. The
converter forms a small but important part of a larger product. Initially I
built numerous prototypes. These were subjected to tests aimed at exceeding
real world conditions as thoroughly as reasonably possible. While the real
environment would not reasonably conceivably allow large input transients
the converter has been subjected to anything you can reasonably do with a
lab power supply and various pieces of wire, string, duct tape and the other
contents of a well equipped electrical workshop. It has also been through
extensive operation within the target equipment in real conditions both here
and in Taiwan. Then it was trialled in about 50 advance test models
(supplied for initial evaluation and to allow torture testing by the systems
integrator). It is now in limited production and so far 2000+ of these have
been built, production tested and accepted by the Customer. So far none of
the converters has misperformed in any way. There have been no failures of
the converter (or, I'm pleased to report,  of the other electronics that I
designed), Due to the relatively "gentle nature" of  buck converters
generally * this design has operated up to the specified voltage rating of
the power FET - not something I would ever wish to see done in real world.
(On such occasions I kept waiting to see what colour the escaping smoke
would be but so far none has escaped captivity).

Ideal design? - No.
Met objectives so far? - Yes.
Useful elsewhere? -  Certainly!
Best design in all cases? - Certainly not!!!


/First, I strongly suggest you do something about that Zener diode and
/its low operating current.  At the very least, test a large number of
/units (with various manufacturer's diodes) at Tmax and verify your
/regulation doesn't go all to pot.  Operating Zener diodes at only a
/few score microamperes reverse current is asking for BIG trouble if
/you're expecting them to maintain their specified breakdown voltage,
/even at room temperature.

"Doing something" about the zener would conceivably somewhat improve the
regulation but the spirit of the original design requires that any such
change is a low cost one. Adding a resistor to ground from the anode of
ZBUK1 (to increase zener current) would assist. Moving PBUK1 from the lh
side to the rh side of RBUK1 and reducing its value substantially would
achieve the same result. Neither change alters the core concept.

DISCUSSION ONLY:    You made this point several times before - then as now
your point is taken.
This is not using a zener in its more normal reference manner. As already
discussed, there will be some 2nd order effects due to operating it further
down the "knee" than usual. BUT - and I'm sure you know this - the rated
voltage for a given zener diode is in fact an arbitrary value set by the
desire to push it as high up its exponential operating curve as possible
(steeper = better here as you note) and the desire to keep the current low
compared to eg device maximum ratings and to minimise self heating. If you
plotted the zener voltage/current curve with say 1mA or 100 uA as full scale
voltage rather than the more normal 10's or 100's of mA as full scale then
the shape of the curve would be remarkably familiar - this is what
exponential curves are about - the rate of increase of the value is
proportional to the value so the curve has the same intrinsic shape at all
scales.


/And second, take a close look (I'd suggest a VERY close look) at the
/effects of output capacitor ESR.  Because of the unique manner in
/which this circuit operates, I think you're going to have major
/problems keeping your operating frequency within tolerable bounds if
/output capacitor ESR goes over a few milliohms.

I believe this is much less critical than you suggest. (But see rough
calculations at end).
You didn't say whether you had determined this from your own consideration
of the circuit or from a simulation - if so a commentv on results obtained
would be interesting. This point can be demonstrated (or not) in practice in
due course if desired. I have used a wide range of capacitor values in this
location including devices obtained from a range of sources (here and in
Taiwan). Operating frequency is not critical in this design and varies over
a very wide range with load (unless a minimum load is set). This tends to be
true of all buck converters unless they have a "sleep" mode where they turn
off completely in low current operation. (This circuit does in fact "sleep"
but less formally than in a circuit with an IC based controller where such a
function can be explicitly implemented by a purpose designated "building
block" - you can only do so much with 3 transistors.)  A full t_off
derivation would be remarkably complex for such a simple circuit (function
of Vin, Vout, load current, Inductance, Cout, R_effective for various
components (inductor, switch, output capacitor, more ...), prior cycle
history and where in the last cycle the converter was when Vout_design was
reached and turnoff started. The latter is important as the amount of
voltage rise after turnoff depends on the portion of energy stored which is
delivered AFTER turnoff starts which depends substantially on where in the
cycle this occurs. This factor alone will swamp quite substantial changes in
capacitor ESR. Certainly, output capacitor capacitance alone has a
substantial affect on toff and the ESR of Cbuk2, which affects dVout sensed
due to I_Cbuk2 dropping across the ESR during charge and discharge.
A rough theoretical calculation suggests that these effects are of a similar
order (unless I lost a few powers of 10 along the way).
. [[[ With a few unstated assumptions: If ALL ring energy was saved in C
then L * Ipk^2/2 = C(Vend^2-Vstart^2) = C(Ve-Vs)(Ve+Vs) ~~ 2VavgC  * dV
or dV = ~~~ (L * Ipk^2) / (4 * Vavg * C)
dV due to ESR is in the order of 2 * Ipk x ESR. Equating
ESR =~~ Li/*8VC) for similar effects.
No doubt someone will point out where/if I went astray - not something i
want to spend too much time on just now. Maybe later after some more
practical results demonstrated.  ]]]


Summary:

Low cost.
Simple design.
Breaks several "rules"
Wide frequency range.
Reasonable performance.
Works well in practice (so far).
Docile and forgiving behaviour (so far).

Core design could be improved by better circuit design without changing core
concept.
Core design could be improved by changing core concepts, almost certainly
with increased cost.

regards


                Russell McMahon

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