Al Williams wrote:
>
> Hmmm... I'm a little bleary eyed, but I don't think INDR works that way.
> INDR is one of those magic registers that is in every bank. So it doesn't
> matter what RP0,RP1 is set to, INDR is always [FSR].


FSR cannot access banks 2 and 3 without considering the STATUS IRP bit.

0 = banks 0 and 1
1 = banks 2 and 3

Of course, this only applies to PICs like the 877 with 4 RAM banks
available.

--
Best regards

Tony

mICros
http://www.bubblesoftonline.com
mailto:sales@bubblesoftonline.com

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