It seems to me that we all seem to be getting a bit too wound up over this. I won't address every point in Dave's last few posts commenting on my comments on his comments on my .... :-) . I should be working so will just make a few overall comments. I assume that our mutual aim os to advance the useful knowledge available in this area. I am reasonably conversant with the technical aspects that are involved in the various circuits that have been discussed and Dave obviously is too. . I am aware that there is no "magic" involved in any of the circuits - just "ordinary old physics". The circuit that I provided is by no means an optimal one if you are wanting highest efficiency, cleanest waveforms, lowest losses, controlled frequency or even well a defined operating point. It is however a superb solution for some applications. RM >The high side drive is no better (in fact no different) than in my circuit >and would benefit from the same optimisations if a FET was used as high side >switch. (eg a bipolar high side FET driver). Dave /If he were to use a MOSFET as a switch, then something would indeed /have to be done- just as in your circuit- to give a more positive /turn-off, or efficiency would suffer greatly. /However, why would he use a MOSFET? How would the design benefit? /Would it improve the efficiency at all, at the low output currents /we're dealing with here? Would it lower the cost? What's the /benefit? Very little potential benefit at the power levels we are talking about (and as per original spec). It was a general comment relating larger to higher power applications. I also noted that my circuit could be (and has been) used with a high side bipolar transistor. At high power and/or high voltage levels A FET can be advantageous. >As well as Dave's suggested changes It would be worth trying removing R9 >(replace with O/C) and R2 (replace with S/C). >This would remove the resistive hysteresis and end up with the same >hysteresis system as in "my" design. /As Richard has already pointed out, this would merely render his /design a linear regulator; under most conditions, it would not /oscillate. Maybe. You may be surprised. The sdame argument applies to "my" circuit. See below re hysteresis. /R2 and R9 are important. A properly designed switching regulator /employs hysteresis as a means of exercising explicit control over both /operating frequency and output ripple voltage. .... /*** big snip *** Agree. But hysteresis does not necessarily have to be achieved by more traditional means - as long as the means used are technically valid. The phrase "properly designed" is a key one here. My circuit is not well characterised. By the nature of the predominant feedback mechanisms it would be difficult (but not impossible) to design it for a given frequency of operation etc. This may be unacceptable in some applications but not in all applications. /Several of us have pointed out, Russell, that your circuit does not /employ hysteresis as a means of governing its operation; yet you refer /once again to the "hysteresis system" in your design. /**snip** /.. (If you continue to insist it does, /then could you tell me what the two hysteresis thresholds are, and the /equations- rough approximations will do- that govern them?) I think the difference is one of semantics. Hysteresis is the condition where a state change which is triggered by an increase (say) in a variable alters the condition under which state change occurs so that the variable must be decreased below the original trip point before the system will again revert to its original condition. (The same applies for a transistion in the other direction). I assume that you accepot this as a reasonable definition of hysteresis. It does not say anything about HOW the effect is achieved. Importantly, it does not say whether the state changes are static or dynamic (ie whether time plays a part in the mechanism). A purely resistive hysteresis mechanism is static. A reactive mechanism may be dynamic but still meet the definition in letter and spirit. Hysteresis is most normally effected by a resistive feedback mechanism where the reference point is shifted by negative feedback from the system output (so that the reference level is reduced when the output goes high and increased when the output goes low. (A typical example is the common single opamp oscillator with resistive feedback to a reference on the inverting input and what can be seen as negative feedback to a capacitor on the non-inverting input). If this is what you understand as hysteresis then my original circuit has got it. The mechanism is NOT the normal resistive feedback version. I have described the mechanism in a previous post. The circuit ALWAYS turns on due to turnon bias from Vin. The inductor current always increases. Vout always rises. There will come a point where the detection threshold is reached. Turn off will start. Energy delivery to the output from Vin will start to decrease. *** BUT *** energy delivery to Vout will continue to INCREASE as energy stored in the inductor will be delivered to Vout. The output capacitor voltage will continue to rise.due to stored energy. The mechanism driving the turnoff will be driven harder even though the system is turning off. This is NOT a usually predominat mechanism for controlling turnoff. Using an infinite value of output capacitance will kill this loop. As it would kill any loop that relied on output voltage evariation for its trip mechanism. This is hysteresis (even if not as we normally implement it, Jim) - Vout continues to rise enhancing the turnoff even as turnoff proceeds. A similar mechanism occurs at at turn on. Notice that on my original circuit I explicitly addressed this means of hysteresis by adding a capacitor which was charged when the reference zener conducted and which continued to hold the FET drive circit on for a period after the zener stopped conducting. Somebody (?Dave?) said that it was "in the wrong place". If you want it to take part in the above described mechansim it is in the correct place. In practice it is not in fact essential to circuit operation. If you have some other role for it then it maybe should be somewhere else. . Re how nactively this circuit oscillates. - "try it, you'll like it". I don't know how it works in SPICE but in practice it starts as cleanly as any oscillator I have ever seen - immediate sharp transistion from linear mode to full clean oscillation. Always full amplitude or no oscillation at all. No intermediate sluggish startup states. Look at a PIC oscillator sometime and see how poorly it starts under some conditions of voltage and capacitance. No similarity here. It's going or it's not. I haven't looked at it on a storage scope but I suspect it has a 1 cycle startup transition. >Also, for higher input voltages consider driving D1 (now a zener as per >Dave's changes) from the OUTPUT via a resistor and tapping the emitter of Q1 >off a resistive divider off the output. Now a high value of resistor from >Vin to D1 will initially bias the zener on and once the system starts, zener >current will be provided from Vout. This reduces the otherwise not >insignificant power taken by the zener bias current. /While in principle this can work, in practice the impedance presented /by the divider (which appears as an Re in series with the emitter of /Q1) will likely reduce the open-loop gain enough to kill oscillation. /etc Maybe. I understand what you are saying but I suspect it can be made to work well. I'll try it some time and report back. regards Russell McMahon -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.