Russell McMahon wrote...

>The high side drive is no better (in fact no different) than in my =
circuit
>and would benefit from the same optimisations if a FET was used as high =
side
>switch. (eg a bipolar high side FET driver).

If he were to use a MOSFET as a switch, then something would indeed
have to be done- just as in your circuit- to give a more positive
turn-off, or efficiency would suffer greatly.

However, why would he use a MOSFET?  How would the design benefit?
Would it improve the efficiency at all, at the low output currents
we're dealing with here?  Would it lower the cost?  What's the
benefit?

>As well as Dave's suggested changes It would be worth trying removing R9
>(replace with O/C) and R2 (replace with S/C).
>This would remove the resistive hysteresis and end up with the same
>hysteresis system as in "my" design.

As Richard has already pointed out, this would merely render his
design a linear regulator; under most conditions, it would not
oscillate.

R2 and R9 are important.  A properly designed switching regulator
employs hysteresis as a means of exercising explicit control over both
operating frequency and output ripple voltage.  And in the context of
switching regulators, "hysteresis" denotes a bistable circuit with two
distinct voltage trip levels: when the output voltage reaches the
upper threshold, the switch turns off; and when the output voltage
drops to the lower threshold, the switch turns on.

These two threshold levels are distinct and they are explicitly set by
component values, and these are established by calculation.  In the
case of Richard's circuit (as modified in my previous post), the upper
threshold is

   Vthupper =3D Vz(D1) - Vbe(Q1) + [Vin * R2 / [R2 + R9]]

and the lower threshold (assuming discontinuous conduction) is

   Vthlower =3D Vz(D1) - Vbe(Q1) - [[Vz(D1) - Vout] * R9 / [R2 + R9]]

which, given R9 >> R2 and Vz(D1) ~ Vout, simplifies approximately to

   Vthlower =3D Vz(D1) - Vbe(Q1).

In practice, the output voltage moves outside these threshold levels.


On the positive side, the output voltage will continue to increase
after the switch has been turned off until the current in the inductor
drops down to the level of the load current, whereupon the output
voltage will reach its peak and then start to fall.  On the minus
side, the output voltage continues to fall below the lower threshold
voltage until the current in the inductor builds up to a value greater
than the load current, at which point the output voltage starts to
rise again.

Neither of these effects is magic, and both can be calculated knowing
the input voltage, output voltage, load current, inductance of the
inductor, and capacitance of the output filter capacitor.  It's pretty
straightforward, if a little laborious.

Several of us have pointed out, Russell, that your circuit does not
employ hysteresis as a means of governing its operation; yet you refer
once again to the "hysteresis system" in your design.

One more time: your design does not- repeat **NOT**- employ hysteresis
as its mechanism of oscillation.  It starts out as a linear feedback
system which, because of its high open-loop gain and the large phase
shifts in its feedback path, is, shall we say, "unconditionally
unstable".  Oscillation starts small and builds up intensity until,
finally, this erstwhile linear system is now alternating, more or less
abruptly, back and forth between two more or less saturated states.
At this point, it is best characterized as a "ring oscillator": like
an oscillator constructed from three logic inverters connected in a
ring, its frequency of oscillation is governed by delays, which in
turn are determined by a variety of factors- including component
characteristics which aren't terribly well controlled.

Yes, your circuit oscillates; and yes, over a fairly wide range of
input/output conditions it appears to function fairly well as a
regulator; but its operation has nothing to do with hysteresis nor
does it exert the explicit control over frequency and output voltage
ripple which hysteresis does.  (If you continue to insist it does,
then could you tell me what the two hysteresis thresholds are, and the
equations- rough approximations will do- that govern them?)

>Also, for higher input voltages consider driving D1 (now a zener as per
>Dave's changes) from the OUTPUT via a resistor and tapping the emitter =
of Q1
>off a resistive divider off the output. Now a high value of resistor =
from
>Vin to D1 will initially bias the zener on and once the system starts, =
zener
>current will be provided from Vout. This reduces the otherwise not
>insignificant power taken by the zener bias current.

While in principle this can work, in practice the impedance presented
by the divider (which appears as an Re in series with the emitter of
Q1) will likely reduce the open-loop gain enough to kill oscillation.
The upper divider resistor could, of course, be bypassed with a
capacitor to reduce the effective series impedance between the output
and the emitter of Q1; or the divider resistance values could be
decreased to similarly restore the gain; but I question whether the
net decrease in Zener bias power wouldn't be offset by that consumed
in the divider.

>I realise that anyone who hasn't looked at and modified the circuit =
diagrams
>will be unable to make any sense of this. I'll try to get to post a GIF =
of
>this 'shortly" unless someone else beats me to it. Dave?

See attachment.

Dave

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