Byron, Could you publish some performance figures for your version of this design which indicate eg efficiency and regulation. Measuring Vin, In , Vout and load for a few values of load would be interesting. Also frequency of operation at various loads. Also note that Vout would best be measured between near the cathode of zener ZBUK1 and regulators own ground as at the currents you are using lead drop can be significant. > Understood. And if we only pull the base up to Vin, then we'll not get the > emitter very close to Vin. In fact it'll end up several volts below. Yes > >>I guess my only question out of this is whether or not it is possible to > >>oversaturate the base. > > > >You can damage the transistor by providing too much base current. This is > >seldom a problem in practice in low power circuits. > >A saturated transistor takes longer to turn off and some high speed > >switching designs use reverse schottky clamp diodes from C to B to prevent > >the transistor fully saturating. This is not applicable here. > > I was asking this question in the context of the 20 to 1 input voltage > Since the base is pulled above Vin and some base resistor will current limit > how do you design so that you don't fry the transistor and yet provide enough > base current to get to saturation at lower Vins. Same problem in designing RBUK3 and RBUK4. Short of providing a second switching regulator to provide a constant drive voltage to the high side driver (oh no!!!) you just have to design for enough drive at worst case and enough dissipation at highest Vin. With a FET this is not hard as the drive current requirements are minimal. With a bipolar itr can be annoying. There is in fact an interesting characteristic of the secondary buck coil volatge which makes this easier. As Vin increases the average voltage of the FORWARD pulses tends to stay constant as their peak voltage increases but their duty cycle (of course) decreases. careful rectifier and smoothing design so you get the average voltage (and not the peak) can mean that high side drive voltate stays fairly constant. This wasn't the sort of thing I felt should be introduced with the basic design :-). > >Summary: It's NOT a darlington - look again and you'll see ot's a little > >unusual. and look at the drive polraity required by the pass FET/transistor. > > Duh. It took me a while to see that absolutely everything is reversed from > the N-channels that I'm used to using. Source is positive, Drain is negative, > Gate must be more negative than drain to get the part to conduct. Duh here too - I thoughgt you were referring to my lower circuit where QB1 turns off Qb2 - also not a darlington and more or less the image of ther FET gate turnoff circuit. > I also think that I figured out that RB3 is a current limiting resistor for > high Vin. I'm testing with 12-15V Vins. I left it off in my prototype. Yes. You really always want a resistor there although ideally it will be much smaller than I have shown for low Vin voltages. > >HOWEVER if the FET was an N Channel then this would work as desired. > >However, we would then need to drive thre FET gate ABOVE Vin during FET > >turnon and so need a high side supply. (as when on FET drain and source are > >connected so source is at Vin so gate must be at leat Vthreshold above Vin > >(plus a bit more). > > The bit more is based on the current passing through the device. I saw an > equation like Rds*Ids... No - more than that. A FET has arated threshold voltage . Apply a voltage less than this to the FET and it will not conduct at all (essentially). Once gate voltagev exceeds Vthresh the FET starts to turn on but it does not do so fully until you gate a gate voltage several volta slarger. Typically for modernish N Channel FETS Vthreshold is 3 to 7 volts. The datasheet will have a family of curves plotting the drop across the FET against various currents with a curve for each value of gate voltage. You will see that for small values of gate voltate the curves "knee" quite early on and above certain values of drain current the drain-source voltage rises quite steeply. This is not usually something you want to happen :-). As gate voltage goes up the cirves become closer to sloping verticalsih lines - ie the FET is beginning to look like a pur resistor across its operating range. You want enough gate voltage to keep the Rdson low during operations so dissipation stays low so we all get home to dinner OK. > After reading (and gaining some understanding) I rushed out and bought parts. > I have an IRF9540 P-channel (Ids=19A, Vds=100V, rDS=0.2 ohms), a 10 microhenry > 11A coil, a 330 uF cap, and a SB580 5A ultra fast schottky catch diode. > Since I wasn't concerned with high Vin, I used ordinary 2N2222 for both > transitors. I also dropped the values of all of the resistors since I'm not > worried about a high Vin. My concern was getting a bit better snap off on the > FET. I bought a handful of different types of zeners, but ended up using a 5V > one. I'm still trying to get clued in on why the output voltage isn't 5.6V > as you specified but 5.0V right on the mark. > > I'm pleased to report that it was a total success. Once I added RB2/QB2 and > got the FET leads straight, Vout is right at the 5V mark. > > I did some preliminary high current testing. Built a dummy load out of 4 > 0.7 ohm 25W ceramics, wired in series/parallel to give a 0.7 ohm 100W load. > Final result: Vout=4.75V @ 7.8A !!! A total success. > > Next up is building a similar boost regulator to get 12V out even with a 6.5V > input. I may even try wrapping that second coil so that I can get a low current > -12V. > It does. I've been trying to get switchers under my belt for a while. Your > design and this thread has taken me several light years further than where > I was. I really appreciate it. Excellent - now you can start on non-divinely inspired arcane "real" ones :-) !! regards Russell McMahon -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu