From: "Olin Lathrop" > Hmm. You've tested this and found it to meet your needs, but there are a > few points nagging me about this design. I guess you get away with most of > these issues because the currents are so low. Here are some issues: This was the design I started with and I embellished it slightly for my final application but it does work very well indeed as shown. Specific component values need to be adjusted for the particular application but its fairly forgiving. RBUK4 is sized fro the circuit I snipped this from and could be rather lower. > 1 - There is no hysteresis in comparing the output level with the desired > threshold voltage. I was worried about this apparent lack for quite some while - it's why I would never have thought the design up by myself :-). I was quite unconvinced that hysteresis was present. However, the inductor in the loop is what makes it work. While you could conceivably very very very carefully adjust things so that the circuit was in a linear mode and there was no increasing current in the inductor, in a real world I believe it will never happen. Took me a while to become convinced however. In practice you can raise the supply voltage as slowly and smoothly as you like and when it reaches design point it transitions cleanly into oscillation. I have tried VERY hard to make this circuit fault as it cannot afford to ever do so in practice. I have so far never managed to do so. > Although unlikely, there is no guarantee this will > oscillate at all. It could, in theory at least, revert to being a linear > regulator. A little bit of feedback from the collector of QBUK2 to the base > of QBUK1 would guarantee instability and also make sure the FET gate is > being driven to the extremes. I tried various feedforward arrangements but none improve results. I will post the full actual circuit I am using some time soon. Main difference is 1 more transistor for FET drive (as mentioned before - improves waveform) and a current limit (which isn;'t needed.) > 2 - CBUK1 doesn't belong there. It will make the regulator slow to turn > on in response to a voltage drop. Largely agree. That was the intention. The point was to add hysteresis by maintaining QBUK1 off longer than otherwise but in practice it is in fact unnecessary. In practice it can be small or even non existent. > 3 - The comparator is two cascaded common emitter stages with passive > pullups. These are going to be slow to respond, asymmetrical, and have a > low slew rate. Only the slow speed of the second is important as it affects FET drive waveform. Slow QBUK1 turnoff slows QBUK2 turn on and FET turn on. These are adequate in practice. FET turn off is more problematical and is addressed in practice by lower RBUK4 or a high side driver (see separate post). At low powers these are not as important. The circuit shown is intended for lower power levels. RBUK4 could indeed be a lower value. The division of voltage by RBUK2/RBUK4 will limit the lower voltage the circuit will operate at due to the FET Vgs threshold. Using a bipolar instead of the FET minimises this. > 4 - The FET will turn off very slowly because the only thing driving the > gate is a 100K resistor. agree > This means the FET will spend a proportionately > long time in the transition region. agree > This may be OK in your situation, but > in general this reduces efficiency and dumps power into the FET. This would > definitely be a problem if the current or input voltage requirements were > increased. Yes. OK for low power. See only slightly more complex circuit for higher powers. regards Russell McMahon -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.