> The PLL suggestions seems tricky. I remember a thread about
> some major PLL-problems a few weeks back... Ill take a quick
> look at it just to see whats involved :-)

I think an analog phase locked loop might be a bit tricky here due to the
large dynamic range of the frequencies it would have to lock to.  However, a
PIC based digital PLL-like algorithm looks pretty straight forward.

The algorithm has three main parts, an input pulse detector, and output
pulse generator, and a output pulse error counter.  Whenever an input pulse
is detected, the pulse error counter is incremented by the number of output
pulses desired for that input pulse - 8 in your case.  Whenever an output
pulse is generated, the counter is decremented by one.  Output pulses are
generated from a free running pulse generator that has an adjustable period
value.  The error counter is low pass filtered and used to nudge the period
in the right direction.  For stability, you may want to take the derivative
of the low pass filtered error counter into account when nudging the output
pulse period.

Note that none of this requires accurate measurement of the frequencies.
You can do all this easily without a CCP module.  The oscillator frequency
also doesn't matter as long as it's fast enough to allow for the necessary
crunch power, which isn't much.  In fact, this looks like a perfect
application for a 12C508A running on its internal RC oscillator.  At 4MHz
clock you still have over 1200 instructions per half period of the highest
output frequency (400Hz).


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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