----- Original Message ----- From: "Dan Michaels" To: Sent: Monday, August 06, 2001 12:32 AM Subject: Re: [PIC]: ?????????/ What is it > Bob.A wrote: > > > > >The point I was making here is that using a (conventional silicon) diode, > >and the R-2D, R-2D limiter you are still stressing the chip pins at greater > >then 0.3V, which is their specified absolute maximum rating. > > > >Now, I know that in reality you have limited the current to no worse than > >0.6V/R in the second stage, but this is still, apparently, out-of-spec. > > > [hint - with no topic/etc, I couldn't even find the thread this > is listed under]. Sorry... I responded to a response to my original post that didn't include a subject! > I don't understand what the argument is here. Seems to me a > 2D-R --> pin protection ckt is perfectly correct, as long as R > is chosen to limit the max current into the clamping diodes on > the pin to a safe value. Chose R > 20 ohms [0.6v/0.025A], and > go. You will "never" actually see Vcc+0.6v on the pin, due to > the IR drop. The issue in this thread is that the pin is specced for 0.3v above Vdd, and before the internal clamping diodes 'kick in' you can have more than 0.3v. > I have a more interesting question, however. > > Say you use the 2D but no R. And say you overvoltage it, and > run too much current thru the internal diodes, and blow them. > Well, you still have the external diodes there, and seems they > will forthwith protect the chip from the stresses the built-in > diodes where in there for in the first place - ESD. And they > will certainly be much more robust than the internal diodes. > > No ????????/ [any takers?] > > - danM > =============== > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics > > -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics