From: "Andy Jancura" To: Sent: Sunday, August 05, 2001 4:57 PM > Hello Bob, > > >A typical circuit uses two resistors in series and adds silicon diodes > >to clamp the junction of the resistors to Gnd and Vdd, thus limiting that > >junction to the range Vss-0.6 to Vdd+0.6 or so. This is _still_ out of > >specification for the PIC pin! > in this case you have cascaded R-2D, R-2D (the second 2D inside the chip), > so the second R has limit only 0.3V from 0.6V at the first stage. If this > isn't o.k. you can still choose schottky. But the questions should be : > which voltage are you protecting the pins from? Depending on the answer, you > should go different ways. > > Andrej The point I was making here is that using a (conventional silicon) diode, and the R-2D, R-2D limiter you are still stressing the chip pins at greater then 0.3V, which is their specified absolute maximum rating. Now, I know that in reality you have limited the current to no worse than 0.6V/R in the second stage, but this is still, apparently, out-of-spec. Bob Ammerman RAm Systems (contract development of high performance, high function, low-level software) -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads