Folks,

I have been converting several 16F84 code files to run on the (cheaper)
16F627 parts.  This generally seems to be a trivial task as the spec of
the F627 is a superset of that of the F84, but it seems to me that there
are some key differences which may be "gotchas" for the uninitiated.

I haven't seen a "minimum checklist" of points to resolve during this
conversion, so I thought I'd share my own list and invite comments:

1.  General purpose registers start at 20H instead of 0CH.

    (ACTION: Change CBLOCK start addresses and any other relevant
     equates accordingly)

2.  General purpose registers are not mapped across into all Banks
    (except for 70H-7FH and its images).  For example, on the F84, one
    could assign a register with a Bank 0 address and assume that it
    can still be accessed when RP0 is set.  On the F627, the change to
    RP0 will cause a different register to be accessed!  In particular,
    this is an issue for interrupt service routines for the F84 which
    "doesn't care" about the state of the bank select bits on entry.

    (ACTION: Check and correct any register accesses which occur while
     bank bits are set to non-default values.  Change interrupt service
     routines to either use shared RAM (70H-7FH) for temporary storage,
     or implement solution described in section 14.7 (Example 14-1) of
     F627 data book)

3.  CMCON register must be initialised to 07H after reset to ensure that
    digital I/O (instead of comparator input) is enabled on RA0-RA4.

    (ACTION: Add CMCON initialisation code to start-up routines)

4.  EEADR and EEDATA registers have moved from Bank 0 to Bank 1.

    (ACTION: Change positions of "BSF STATUS,RP0" and "BCF STATUS, RP0"
     instructions in EEPROM read and write code fragments) (*)

    (N.B. My copy of the 16F62X data book ("Preliminary") appears to
     have implemented this change in Example 13-2 (Data EEPROM Write)
     but not in Examples 13-1 and 13-3)

5.  EEIE bit has moved from INTCON register (accessible from any Bank)
    to PIE1 register (Bank 1 only), and EEIF bit has moved from EECON1
    register (Bank 1 only) to PIR1 (Bank 0 only).

    (ACTION: Change BSF/BCF instructions accordingly and ensure Bank
     bits are set correctly before attempting to access these bits)

6.  PROCESSOR (or LIST) directive needs to be changed from 16F84 to
    16F627, and __CONFIG directive needs to include _LVP_OFF (to free
    up RB4) and _BODEN_OFF (for strict F84 compatibility).

    (ACTION: Change directives as indicated above)

As I understand it, CMCON is the only special function register that is
"new" in the F627 which needs to be explicitly initialised after reset
to ensure F84 compatibility.  However, there may be a case for explicit
initialisation of other registers for extra robustness - any views?

Obviously, I haven't attempted to cover above any code optimisations
that may be possible given the greater resources of the F627 (more RAM
and EEPROM, on-chip USART etc.).  I have just focussed on getting the
F627 operating as a "drop-in replacement" for an F84.

Have I missed anything?
--
Ian Chapman

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