> Dan:
> Thanks for the comments.
> 1)I'm aware of the constitution of the 10 bits of duty, but my question is
> why?  If the period reg is 8 bits, any set of bits 9 and 10 at any time
will
> yield 100%.  Do I have that right?

No: because bits 9 and 10 are really bits -1 and -2. What I mean by that is
that they are the least significant bits of the duty cycle, and can be
considered fractional bits relative to the resultion of the period.

This is because each count in the period register actually maps to 4 clock
cycles (one instruction cycle). The extra PWM bits let you resolve to the
individual clock cycle.


Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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