>>
At 4MHz, that's orders of magnitude away from a 1s delay, and I would like
to have delays of 24 hrs or more!  The only way I can think of getting
around this is having the interrupt routine increment another register, and
be able to count the cycles to a second that way.  But again, that's a very
inconvenient way if you want a routine to function every 24 hrs, you would
need quite a lot of bits!
<<

Gimme a break!  This is quite simple and is done all the time.  The maximum
timer 0 overflow rate is once every 65,536 instructions, or every 65.536mS
at 4MHz oscillator.  That is 15.26 times per second, so it only takes a 4
bit counter to get to a second.  For 24 hours you need to count to 60 * 60 *
24 / 0.065536 = 1,318,359, which requires 21 bits, which requires only 3
bytes.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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