Rather than use a shadow register, I'd use a shadow CONSTANT TRIS_SHADOW = 0x?? ; whatever you need for non-I2C pins movlw TRIS_SHADOW |(0x01 << SDA) ; make SDA an input tris GPIO movlw TRIS_SHADOW ; make both I2C pins outputs tris GPIO This technique will work well if you do _NOT_ change the in/out characteristics of any other pins while running the I2C code. Otherwise you might need the shadow register technique. Bob Ammerman RAm Systems (contract development of high performance, high function, low-level software) ----- Original Message ----- From: "Garber, Mike" To: Sent: Monday, July 09, 2001 11:25 AM Subject: Re: [PIC]: 12CE5xx & FL51XINC.ASM & Internal EEPROM > What I mean is this: Within FL51XINC.ASM are lines such as - > > movlw (0x01 << SDA) ; make SDA an input > tris I2C_PORT > and > movlw 0x00 ; make sure both are outputs > tris I2C_PORT > > (this is really indended to configure 2 bits of the single GP I/O port > but if I wanted some other bits to be inputs, this code snippit would > change them to outputs, right? Also, I see in section 4.4 of the 12C5XX > data sheet that setting a TRIS bit to '0' would disable the wake-up on > change, and weak pullup function for the corresponding pin). > > So, wouldnt the "correct" way be to assign a shadow register - > cblock > TRIS_SHADOW > ... (other data registers) > endc > > {along with some bit definitions - > GP0 EQU 0 ;I wanna use this as an input > GP1 EQU 1 ;I wanna use this as an input > GP2 EQU 2 ;I wanna use this as an output > SDA EQU 3 ;Bi directional > } > > and in my main code - > movlw (0x01 << GP0) | (0x01 << GP1) ; GP0 & GP1 an input > movwf TRIS_SHADOW > tris I2C_PORT > > and when I want to make SDA and input - > movf TRIS_SHADOW, w > iorlw (0x01 << SDA) ;generate OR mask > movwf TRIS_SHADOW > tris I2C_PORT > > and when I want to make SDA and output - > movf TRIS_SHADOW, w > andlw ~(0x01 << SDA) ;generate AND mask > movwf TRIS_SHADOW > tris I2C_PORT > > > Or is this really overkill? > Thanks > > Mike Garber > > > > > > > -----Original Message----- > > From: Dwayne Reid [mailto:dwayner@PLANET.EON.NET] > > Sent: Saturday, July 07, 2001 1:52 PM > > To: PICLIST@MITVMA.MIT.EDU > > Subject: Re: [PIC]: 12CE5xx & FL51XINC.ASM & Internal EEPROM > > > > > > At 04:38 PM 7/6/01 -0400, Garber, Mike wrote: > > > > >Also, I notice that within FL51XINC.ASM, the TRIS instruction is used > > >repeatedly. > > >Shouldnt a better way be to use a "shaddow" register to hold > > the value > > >sent, so that > > >the configuration of GP0 thru GP5 doesnt get screwed up from > > the direction > > >I want > > >them to be from my main program? > > > > The 12c5xx parts use the 12 bit core. Thus, the ONLY way you > > can change > > the TRIS bits is to use the TRIS instruction. > > > > dwayne > > > > > > > > Dwayne Reid > > Trinity Electronics Systems Ltd Edmonton, AB, CANADA > > (780) 489-3199 voice (780) 487-6397 fax > > > > Celebrating 17 years of Engineering Innovation (1984 - 2001) > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > > Do NOT send unsolicited commercial email to this email address. > > This message neither grants consent to receive unsolicited > > commercial email nor is intended to solicit commercial email. > > > > -- > > http://www.piclist.com hint: The list server can filter out subtopics > > (like ads or off topics) for you. See http://www.piclist.com/#topics > > > > > > -- > http://www.piclist.com#nomail Going offline? Don't AutoReply us! > email listserv@mitvma.mit.edu with SET PICList DIGEST in the body > > -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listserv@mitvma.mit.edu with SET PICList DIGEST in the body