Thanks Vasile. The problem with putting a RC delay in line with the active
low enable pin is that it violates setup and hold times for the 377
(possible metastability problems?). In order to keep the enable line low at
power up, I need a delay of about 1.56 ms; on the other hand, the DSP I am
using toggles the clock and enable line only for about 100ns (during data
write). Any other thoughts?
Thanks
Madhu

-----Original Message-----
From: pic microcontroller discussion list
[mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Vasile Surducan
Sent: Thursday, May 31, 2001 2:14 AM
To: PICLIST@MITVMA.MIT.EDU
Subject: Re: [EE]:74HC377 power-up problem


I don't know the 377, haven't a reset or an enable pin active low?
If yes, use a rc network from vcc to gnd and connect that pin to the
middle of it. The output will stay low at powering up, a time = rxc
Vasile

On Wed, 30 May 2001, Madhu Annapragada wrote:

> I am using the 74HC377 as a data latch in an application. The problem is
> that on power up all the outputs of the 377 go high. The setup is as
> follows:
> All the data input lines to the 377 have 4.7K pull down to gnd.
> On power up, all the data lines to the 74HC377 are low (verified on a
> scope). The clock (positive edge trigger for the 377)and enable
line(active
> low, data is latched to the output only when enable is low and the clock
is
> rising) reach VCC in about 1.2 and 1.6ms respectively. So even if the
clock
> line is latching the data inputs to the output lines while the enable is
low
> at power up, my data inputs are all low. So why are my outputs from the
377
> coming up high? I am using the HP54622 mixed signal scope, and I have not
> been able to see any glitches on the data inputs at power up.
> Any help would be very much appreciated.
> Thank you
> Madhu
>
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