> A SEEPROM is read using bit banged I2C. The SDA line is driven by a
> tristate pin on a MCU (bit banged). The option to simulate an open
> collector output using a tristate pin (by manipulating the tristate
> control) is not available.

This is a bad idea.  It can lead to race conditions and possible power
glitches.  If you have no open collector output available, you can make one
with an NPN transistor and a resistor.

> When reading a byte from the SEEPROM I have the I2C command sequence:
>
> START> - SELECT> - ACK1< - ADDRESS> - ACK2< - READ< - ACK3? - STOP
>
> The last ACK is not important (I never read bursts in this project).
>
> The question was: *when* does the SDA line of the slave turn output and
> back again for:

The slave is allowed to pull SDA low immediately after the falling edge of
SCL of the 8th bit of the address byte.

In general, a bit is over on the falling edge of SCL.  The SDA line is
allowed to change while SCL is low, and must be stable by the rising edge of
SCL.  Most devices clock in SDA on the rising edge of SCL, although it would
be legal to read SDA anytime SCL is high.  Unless you are the master, you
don't know when SCL is about to go low, so it is safer to sample SDA on the
rising edge of SCL.  In my software master IIC routines, I release SCL, then
sample SDA, then pull SCL low again.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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