Peter L. Peres wrote:
>
> > Like any send or receive bit the SDA
> > must be held stable for the entire time the SCL
> > is high, and it doesn't matter when SCL is low.
> > -Roman
>
> It matters because my driver is NOT o.c. If the driver disagrees with the
> SEEPROM then silicon will fight silicon and someone will loose (probably
> the power supply, because this project runs on a single lithium cell). I
> am trying to avoid that.


Peter, that sounds unusual, the master must go
O/C to sense the ack! Unless you are using
a resistor and the master has two PIC pins,
one for send and one for sense.

Anyway I think the answer you are looking for
is that the slave inits the ack straight after
SCL for bit 8 goes low. It must maintain the
ack as low for the entire time of the next SCL
pulse, and after that SCL goes low it can release
it. Page 3 of the 24LC256 eeprom datasheet shows
Taa (eeprom SDA output) takes typically 900nS
to stabilise from the last neg-going edge of
SCL.
-Roman

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