> When a slave device is to transmit its data on the bus *when* does it turn
> output:
> a) after the 8th data bit of the host is sent (when clock goes low after
8th)

If you replace HOST with MASTER, then yes.  At this point the slave may
start driving the ACK bit onto SDA.  The bus must be stable with the ACK bit
by the time SCL goes high.

> c) does it *stay* low or output between this time and when the host raises
> the 1st clock to read a byte from the slave (assuming that the first bit
> to be read is a 0).

Between what time?  I don't know what "this" time is.

On a read, the slave controls SDA after the falling edge of SCL of the
master's 8th bit (which will be high indicating a read).  The slave
continues to control the bus until the end of its 8th data bit, at which
time the master writes the ACK bit to SDA.  Note that "owning" doesn't mean
"driving" since the lines are open collector.

> d) when does the slave release the data line after it has sent the last
> bit of a byte: immediately after the last clock pulse goes low ?

Yes.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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