Even the C and DC are not used as inputs to the ALU, they are latched at the
same time as the rest of the arithmetic result is latched into registers and
must be valid at that time.

Again: why would I want to add even a little bit of silicon to every PIC I
make when it gains me _NOTHING_ in functionality?

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

----- Original Message -----
From: "Peter L. Peres" <plp@ACTCOM.CO.IL>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Sunday, May 20, 2001 1:00 PM
Subject: Re: [EE]: carry result: Robin Abbott


> >It can significantly slow down the CPU because it is in the critical "ALU
> >loop" which you want to make as simple as possible.
>
> Not on the PIC it isn't. The C and DC flags are only outputs and have the
> same constraints as any result-to-register operation. The delay induced by
> the circuit I proposed is 2 gate delays. I doubt that this would upset the
> CPU timing but you can't tell until you try.
>
> Your argument is correct in ALUs where C and DC are both in and out. Then
> they have to be really quick (usually double buffering is used but this
> gives problems with a pipelined architecture - I don't know what they do
> in that case).
>
> By the way, does DC also behave like C in a substraction ? It could solve
> a number of problems I have. I have seen very few algorythms using DC
> anyway.
>
> Peter
>
> --
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>
>

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