>It can significantly slow down the CPU because it is in the critical "ALU
>loop" which you want to make as simple as possible.

Not on the PIC it isn't. The C and DC flags are only outputs and have the
same constraints as any result-to-register operation. The delay induced by
the circuit I proposed is 2 gate delays. I doubt that this would upset the
CPU timing but you can't tell until you try.

Your argument is correct in ALUs where C and DC are both in and out. Then
they have to be really quick (usually double buffering is used but this
gives problems with a pipelined architecture - I don't know what they do
in that case).

By the way, does DC also behave like C in a substraction ? It could solve
a number of problems I have. I have seen very few algorythms using DC
anyway.

Peter

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