> My point is it is making a *lot* of difference--the "wrong" way.  At
    > 19.2k the idle time between bytes is 55us whereas at 38.4k the idle time
    > is about 185us.

    That is what you expect to get with a properly written UART routine (waits
    for ready before writing to TXREG, not after, as Bob pointed out) when the
    rest of the system doesn't produce bytes as fast as they can be sent.

Most uarts have at least one byte worth of transmit buffering (and modern
uarts are likely to have 10+ bytes of transmit FIFO.)  As you're noticing
here, and other people are pointing out, big FIFO don't help if you simply
can't produce/consume bytes quickly enough, they only help if your attention
to the uart is "sporadic."

Lets's say that it takes 1ms to transmit a byte at 9600bps, and your code
can only source bytes every 1.5ms.  At 9600, you'll see .5ms between bytes.
If you increase the bitrate to 19200, each byte will only take .5ms, but
the gap BETWEEN bytes will increase to 1ms...

BillW

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