=
> Bob Ammerman wrote:
> > Perhaps they do prefer #1, but would they prefer it enough to accept a
> > slower maximum clock rate on their PIC because of the additional
> > hardware required in the ALU loop?
>
> The 'additional hardware' consists of a two way multiplexer (or two and
> gates and an or gate to combine their outputs), one of the ands using an
> inverted input. Also a wire from the instruction decoder to select the
> desired carry behaviour (this may be harder than the transistors). I am
> sure that this will terribly terribly slow down the CPU. And add all of
> about 16 transistors to the CPU. Never mind, once you get used to the idea
> that the PIC has 0 C on borrow it's ok.
>
> Peter

It can significantly slow down the CPU because it is in the critical "ALU
loop" which you want to make as simple as possible.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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