Brandon Fosdick <bfoz@GLUE.UMD.EDU> wrote:
>If you're going to use an FPGA, you could get a PIC core from opencores
>and put that in the FPGA too.

Thanks for this.  I realise now that my reference to FPGAs in my initial
posting was misleading as I was originally intending to use something
like a MACH 4 device (i.e. a CPLD) for the DRAM addressing and control
logic.  However, I'll consider this as an alternative approach.

Tom Handley <thandley@teleport.com> wrote:
>[ lots of good stuff... snipped! ]

Thanks also.  I didn't realise that the 6 month Lattice starter licence
could be renewed for *free* - I had assumed that one would be forced to
upgrade to a full licence at the end of this period.  I'll dig into the
Lattice information some more.  On first glance, it looks to me as if it
would be straightforward to modify the ISP download cable to handle 3.3V
(LV) Lattice devices - any experience with this?
--
Ian Chapman

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics