Roman,

> Any suggestions?

You don't say whether you've looked at a byte frame on a 'scope  to
confirm the rise and fall times, and the slew between SDA and SCL.
Is SCL held valid low the whole time SDA slews?  Can you do that
test?  The symptom does sure sound like something is wrong with bit
timing, since you don't read back a correct ACK from the EEPROM.

-Barry.
------------
Barry King
NRG Systems "Measuring the Wind's Energy"
http://www.nrgsystems.com
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