James Lee Williams wrote:
> I want to use only these three signals coming from a pic to control the
> addressing to the ram.  However, I can seem to find any counters with
> this number of address lines.  Does anyone have any suggestions for
> tackling this.  The reason for this, is that I want to be able to read
> data from the ram in not more that 3 instruction cycles.

You can build up the counter with discrete logic, PALs or use a CPLD.

> Also, maybe someone can also give me some suggestions on how to have
> this ram accessable from two different pic devices.  One pic will only
> write to the ram, while the other pic will only read from the ram.
> However, I will in reality have to of these 512Kbyte chips, configured
> in such a way that one pic can write to RAM of chip 1 while, at the same
> time the other Pic will be able to read from chip 2.  The trick here is
> that the the data buses much be able to be released from each Pic or
> inserted.  But never both Pics at the same time.  I have been thinking
> about using a dual bus transciever for each RAM chip.  Then use hardware
> logic to prevent simaltaneous access to the same chip by both
> controllers.  If anyone any clever ideas on this or comments, you input
> would be greately appreciated.

You have not provided much information, regarding:
  will both PICs share the same address generator, (writes on PICa
    to be at same address as reads on PICb?)
  or will you have to control which PIC controls an address generator
    for each the two rams?
  could a single ram be "time sliced" such that during 1 phase PICa
    has access and during the next PICb?
  are there a cost/area/power limits on the design?
  what speed are the PICs running?
  what speed SRAM are you planning?



  A single SRAM and CPLD (or FPGA in the ~$10) range may be handle all
of the above (including data bus separation, dual counters PIC
arbitration, etc.).


David W. Gulley
Destiny Designs

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