Ok Mike now I understand your concern:

In the code:

> Here is my suggestion (this code would be in the interrupt handler)
>
> fudge = ...number to account for instructions timer is turned off...
> magic_value = D'65536'-D'5000'+fudge
>
>     bcf        T1CON,TMR1ON    ; turn off timer
>     movlw   low(magic_value)
>     addwf   TMR1L,F
>     btfsc     STATUS,C
>     incf       TMR1H,F
>     movlw   high(magic_value)
>     addwf   TMR1H,F
>     bsf        T1CON,TMR1ON    ; turn it back on
>
> Also, sorry this is in ASM, not C, but the same thing should work in C.

you are concerned that the BTFSC can introduce jitter. This isn't the case
because:

If the skip is taken the BTFSC will take 2 clocks.

If the skip isn't taken the BTFSC will take 1 clock and the INCF TMR1H,F
will take 1 clock.

Your other question dealt with dejittering timer 2 interrupts on the 18C.
This works because there are only two possible values of timer 2 when we get
into the handler, depending on whether a 1 or 2 cycle instruction was
interrupted. You can tell those two values apart by just looking at the
least significant bit of timer 2.

The same technique should work for the other timers.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

>
> Second posting:
>
> The maximum jitter on a PIC is one cycle. This is because some
> instructions take one cycle and others take two cycles. It is possible to
> completely dejitter the PIC by examining the value of the timer register
> in the interrupt handler. For example, I use the following code on an 18C
> to do exactly that:
>
>  org 8
>
> ; The next two instructions are used to eliminate jitter on the
> ; interrupt timing. When the interrupt occurs, it may have to wait
> ; an extra cycle becuase a two cycle instruction is in progress.
> ;
> ; We can tell the difference by looking at the least significant
> ; bit of TMR2. If the next instruction skips we use 2 cycles, if it
> ; doesn't skip then we use 3 cycles. The net result is that we add
> ; a cycle when needed so that we always get to 'dejittered' at the
> ; exact same time relative to the actual rollover of TMR2!
>
>  btfsc TMR2,0,A
>  bra     dejittered
> dejittered:
>
> Note that this technique should work on all PICs.
>
> Also, on an 18C external interrupts are dejittered by the PIC hardware,
> as noted by this quote from the last paragraph of section 7.0 of the
> 18C452 datasheet:
>
> >For external interrupt events, such as the INT pins or the PORTB input
>  change interrupt, the interrupt latency will be three to four
>  instruction cycles. The exact latency is the same for one or two cycle
>  instructions.
>
> I don't believe that external interrupts are dejittered by any prior PIC
> families. Please correct me if I am wrong.
>
> So, my conclusion is that for timer and external interrupts the 18C can
> process the interrupt with zero jitter. Non 18C chips can do that for
> timer interrupts but not external interrupts.
>
> Bob Ammerman
> RAm Systems
> (contract development of high performance, high function, low-level
> software)
>
> >>
> > I found another entry (by Bob again), where he talks about completely
> > eliminating jitter by looking at the lsb of TMR2.  Why does this
indicate
> > whether or not a 2 cycle instruction is in progress?  Is it the same for
> > the other timers?

--
http://www.piclist.com hint: The PICList is archived three different
ways.  See http://www.piclist.com/#archives for details.