At 09:39 AM 3/8/01 -0600, you wrote:

>>From the comments by Spehro & Olin, is this all hooey??

Not hooey, there are two distinct problems. The first is that the
value for comparison should be double-buffered. If this was not true, it
would be possible to "short cycle" the PWM by writing a value into
there during the PWM cycle. If the (double-buffering) hardware was
not in the PIC, it would be very difficult to make a glitchless
(even) 8-bit PWM.

The second only rears its head when you go beyond 8 bits on the
PWM. The problem is that you have *two* registers being written
at an unknown time relative to TMR2 rollover, if it happens to hit
exactly after the update of the MS 8 bits, but before the update
of the LS 2 bits (or the opposite), you get a glitch. You could imagine a
pathological situation where the program was running isochronously
and *always* hitting at just the right time, and the required PWM
value was bobbling between 00000001 00 and 00000000 11 on alternate
updates. In this unlikely scenario, the output could be steady at
0000001 11 (almost double what it should be) or 00000000 00 (zero).
This happens because the update of the two bytes is not an atomic
operation, this being an 8-bit processor. Some Motorola micros
deal with similar issues by interlocking it so the update of the
comparison register won't take place until the 2nd register is
written if they are written in one order, and allowing the glitch
if they are written in the reverse order. That takes a FF and
a bit of logic on chip.

Thanks for the comments, guys!

Best regards,



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Spehro Pefhany --"it's the network..."            "The Journey is the reward"
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