James Cameron wrote:
>On Wed, Mar 07, 2001 at 11:52:40AM -0500, Dan Michaels wrote:
>> James Cameron wrote:
>> >Looking for archived discussions or sample code to adjust for consistent
>> >drift in my PIC 16F877's 4MHz crystal oscillator.
>> .......
>> >The problem is that my clock is losing one second every three hours.  It
>> >is at least consistently doing this.  It is well within specifications
>> >for the crystal.
>> Your error is ~1/3600, while xtal error is <= 50/1000000 = 1/20000,
>> so the problem is no doubt in your code. 4 mhz is not an even power
>> of 2, so your method of adjusting for timer overflows probably needs
>> to be fixed. Look there.
>
>Ah, maybe I've got one of those off-by-one problems.  I checked most
>carefully ... TMR0 at 1:256, should give one T0IF every 65536uS exactly,
>which I add into a 24-bit counter and then subtract one second.  If the
>result is positive, I keep the new counter value and activate my 1Hz
>code path.  TMR0 runs free, never reset.  Does this logic seem sound?
>
>http://quozl.netrek.org/uptime/uptime.asm is the code.
>http://quozl.netrek.org/uptime/ has the rest of the code.
>


James, in case you didn't see it, I posted a later msg indicating
your actual error is ~1/10000 [I overlooked the "3" the first time
--> sorry], which could correspond to about 100 ppm, or a typical xtal
operating on the edge.

However, when you're using a xtal which is not an even power of 2,
you always run the risk of the off-by-one problem, as you indicated,
so you really have to scrutinize your code. I downloaded your ASM file,
but couldn't really read it as it formatted funny in my editor.

If timing is really critical, as other possible options, I would
suggest using a xtal like 4.096 Mhz, which makes the code more
straightforward, and finding one with 20-30 ppm characteristics.

After everything else is beaten to a pulp, you can always try
the tunable cap in the xtal ckt.

- dan

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