> (4) Must "preload" TMR0 with literal 6 so it will have a cyclic period of
>250 (256-6).  But wait, must compensate by loading TMR0 with 6+2 = 8 because
>the timer increment is latent for
> 2 instruction cycles after a write to TMR0 (see data sheet)

I have a feeling this should be 6 - 2 = 4 because it is a count up timer that
interrupts on overflow, and you need to take account of the number of
instructions in your interrupt routine before you reload it.

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