>
>Then the transisor won't be saturated because the 5V output from the PIC
>isn't high enough relative to the collector voltage.

Nooo. Saturating the transistor is all about how much base current you can
deliver.
The transistor has a gain figure (beta) Collector current = Base current *
Beta, at least in this simple example.


>3) Replace the NPN with a logic level power MOSFET. The MOSFET is completely
>on with an input of 4V. And it has such a high impeadence that essentially
>the PIC is isolated from the output circuit.

Right, because it's a field effect device. (Metal Oxide Silicon Field
Effect Transistor)
However, it still needs current to charge it's gate capacitance.
While that is charging, the fet is partially on, and will heat significantly.
If you don't take too long to get there, and you don't do it too often,
then it's not a problem.



>                   +24
>                    |
>                  Load
>                    |
>                    C
>                   /
>          +-------B
>          |        \
>          C         E
>         /          |
>PIC-R--B         GND
>         \
>          E
>          |
>         GND
>
>Now it looks to me like this won't work because there's no mechanism to
>provide positive voltage to the cascaded base so the second transisor will
>never conduct.

If both transistors are NPN, then yes, it dosen't go.
If the second is a PNP, with the C and E reversed, then you have a Zaiklai
pair.
You'll want a resistor from base to 24V to assure that the PNP shuts off
completely though, and
a resistor from Q1 C to Q2B to limit the base current to something reasonable.


>This is an instance where I'm a computer guy trying to understand some simple
>EE principals.
>
>Any suggestions?

Grab a copy of Horowitz and Hill :)
It's well worth it!


--
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