Another thought to add to my prior response:

Given that the period of the 1KHz PWM is going to be close to 2000 cycles,
it should be possible to optimize the division quite a bit. The dividend
will may out at about 2000*832 = 1664000 which will fit in 21 bits. The
divisor will fit in 12 bits. The quotient will be no more than 10 bits.

Or, you could treat the period of the 1KHz PWM as a constant (say 2000
cycles) and compute your output period as:

period(output) = period(input) * (832/2000)

Using a single, optimized, fixed point multiplication.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads