HI all,
I have a problem that I hope someone has already come across before.
I have a slave PIC (16F877@20mhz) which will be receiving data from a
master PIC (16F877@20mhz) in the system.  This data will be 2 bytes.
Once the data is received, the slave PIC will begin to parse it and
do some math, rounding, ascii conversion and then construct a
sentence using that data plus data the slave has gathered from a GPS
receiver, all used to construct a sentence to then be sent out the
serial port to a PC.  During the time that the data is being made
ready and sent out the RS-232 port I cannot lose any more data that
may be coming from the master PIC.  Therefore I have set up the
communications in the slave PIC to be interrupt driven.  Here's where
the question comes in, is there a way to set up a FIFO buffer using
registers to store the data with some sort of counter to keep track
of it.  I might get 3, 4, 5, 10 or more transmissions of the 2 byte
data from the master fairly quickly and then some time in between
which I hope will give me enough time to catch up and clear out the
FIFO before I receive more.  I know that the FIFO will at some point
have a limit and could overflow and so I would like to make it as
large as I can but if it happens then I will send some sort of
overflow message out the serial port if it should occur.  If anyone
can point me to some info on doing this I would appreciate it, I
didn't see anything in my search.  Any info/advice is greatly
appreciated.
Regards,
Charles

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