Hi Olin,

1. The BIOS necessarily checks the memory by doing a
read-and-write-and-read test. This may output garbage on my output port
but I can deal with this (using a magic key or a timer). It will not
likely recognize the area as ram (the output port will not be
back-readable).

2. The system does not think, the BIOS thinks. I have a Linux driver in
view, and only for chipsets with published datasheets. This means, that I
do not care what the BIOS thinks, as I will do the thinking later, when
loading the driver module, and fudge the chipset paging registers as
required to map the port somewhere. I have done this before with strangely
mapped FLASH ROM (dockable) so I know the ropes a little bit.

3. Dynamic refresh is usually RAS-only refresh. Since I decode CAS and WE
for triggering on output and input, I do not need to be afraid of it. It
will upset the timing but that is a small price to pay for what I can
gain.

4. There is a problem with burst accessed RAM and cached reads. My driver
will have to explicitly flush the cache before and after each access to
the IO-SIMM (see, it has a name already). This can be a problem, but it is
still minor (latency in the low hundreds of nanoseconds probably).

I will keep the list posted but do not hold your breath ;-) So many toys,
so little time...

Peter

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email listserv@mitvma.mit.edu with SET PICList DIGEST in the body