Olin Lathrop wrote:
>There is a small problem in Microchip's current implementation of the MSSP
>module.  The master reads the ACK bit on the wrong (rising) edge of the
>clock line, thereby causing a race condition.  The slave can react to the
>rising edge of clock and release the data line before the master reads the
>data line.  This causes the master to read the ACK bit as a NACK.

Small problem?  That is terrible!

Thanks a bunch Olin, things like this can drive me nuts, and waste a=
 terrible much time.
I have not yet played with IIC, but I will later.

>The work around is to make the RC time constant of the data line longer=
 than
>that of the clock line.  This causes the data line to hold its state for a
>short time after it is realease by the slave.

Smart solution :)

>I personally consider 400KHz now the
>upper limit of the MSSP module in master mode.

OK, we can=B4t have it all...

>And yes, Microchip has acknowledged this problem and will try to fix it in
>future versions of the MSSC module.

Good of them.
As I have told here before, some companies do not acknowledge there ever=
 is/was a problem, but still fix it in later chip release...

I feel more confident with companies like Microchip :)

Did they say anything about fixing the module in existing chips, such as=
 16F87x?
Or will the debugged MSSP only show up in upcoming chips?

Thanks
/Morgan

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