I wrote, according the new design in newer PICs:

>Any port change that occurs between (end of) Q1 and (end of) Q3 will=
 neither be read in by the current read instruction, nor will it generate a=
 new interrupt.

Duh, my hands were typing without brain engaged...

Well, we are already in interrupt service, and the compare register updates=
 the new state during Q3, so we can=B4t clear RBIF until we make new access=
 to the port.  I.e if we try retfie we wil get to the interrupt routine=
 again and then read th eport again, so it solves by iself.

/Morgan

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