Ok, those were garbage, but these work a bit better... The idea is that stuff you need to do with computation on the PC are replaced by a macro that uses some (minor) smarts to A) compile a replacement (like with iread for data lookups) B) put the subroutine entry jumps in the first low half page if the subroutine is not already in the lower half of a code page C) compile jump tables into the first low half page using page selects with each jump only if the addresses it needs to get to are on different pages. As long as there are less than 256 bytes used for the jump to the ISR, the jumps to subroutines not in low half pages and the jump tables, memory will take care of itsself... I think... RESET reset_entry LookupW MACRO noexpand ;Defines an in-line DW/IREAD lookup table which ;returns the 12 bit value indexed by W in M:W. ;Affects M and W. expand jmp @$+\0+2 ; IF \0 _LookupWTableBegin = $ noexpand REPT \0 expand DW \% noexpand ENDR _LookupWTableEnd = $ expand IF _LookupWTableBegin & $FF <> 0 mov temp,w ;WARNING temp modified by macro mov w, #_LookupWTableBegin & $FF add w, temp ;offset from start of table ENDIF mov m,#_LookupWTableBegin>>8 IF (_LookupWTableBegin / $100) <> (_LookupWTableEnd / $100) snc ;correct if carry mov m,#_LookupWTableBegin>>8+1 ENDIF iread ;Retrieve data noexpand ;{use the data} ENDM Subroutine MACRO noexpand ;Usage: Define a Global lable, execute Subroutine, assign :Entry to the value now ;set in SubEntryAddr. Continue the definition of the subroutine. Elsewhere, call ;@Sub:Entry where Sub is the global lable you defined for the subroutine. ;Example ;SUB1 Subroutine ;:Entry = SubEntryAddr ;.... ; Call SUB1:Entry _SubAddr = $ IF (_SubAddr & $100) <> 0 org LowHalfPage SubEntryAddr = $ ;if we got here, the pagesel bits must be set for here IF ($ / $100) = (_SubAddr / $100) expand jmp _SubAddr noexpand ELSE expand jmp @_SubAddr noexpand ENDIF LowHalfPage = $ IF $+1 & $100 ERROR 'Out of LowHalfPage Space' ENDIF org _SubAddr ELSE ;The subroutine was already starting in a LowHalfPage SubEntryAddr = $ ENDIF ENDM GotoW MACRO noexpand _SaveAddr = $ org LowHalfPage _GotoWPage = \1 REPT \0 IF (\% / $100) <> (\1 / $100) _GotoWPage = \% ; ENDIF ENDR IF _GotoWPage <> \1 ;has to be a long jump table IF \0 > 127 ERROR 'Since the addresses are in different pages, long jumps must be used and no more than 127 entries can be supported' ENDIF ELSE IF \0 > 255 ERROR 'No more than 255 entries can be supported' ENDIF ENDIF expand _GotoWTableBegin = $ IF _GotoWPage = \1 AND (_GotoWPage / $100) <> 0 page \1 ENDIF jmp PC+W noexpand REPT \0 IF _GotoWPage <> \1 expand jmp @\% noexpand IF $+2 & $100 ERROR 'Out of LowHalfPage Space' ENDIF ELSE expand jmp \% noexpand IF $+1 & $100 ERROR 'Out of LowHalfPage Space' ENDIF ENDIF ENDR LowHalfPage = $ org _SaveAddr IF _GotoWPage <> \1 ;its a long jump table expand rl WReg noexpand ENDIF expand jmp @_GotoWTableBegin noexpand ENDM org 0 ISR ;(Interrupt Service Routine) ********************** ;put your ISR (or just a jump to it) here. jmp @VPS :Out ;------------------------------------------------- ;The Virtual Peripherals are expected to jump back ; to @ISR:Out when done ; << added to correct bug in 9818 chips mov m,#WKEN_B ;Enable Port B interrupts mov !rb,#rbIntMask mov m,#TRIS ;Point mode back to ports ; end bug fix >> mov !option, #myOpts mov w,#-IntPeriod ;1 retiw ;3 ;retiw adds w to RTCC which avoids ;jitter due to variations in ISR path or latency. TABLES ;*********************************************** ;Jump tables are assembled here by the SUBROUTINE, ; and GOTOW macros. LowHalfPage = $ org $100 ;Leave space in the first LowHalfpage STARTUP *********************************************** reset_entry ;must be in the first page jmp @MAIN org $+2 ;Leave space for the debugger MAIN ;PROGRAM ***************************************** GotoW Main, $800, ISR, SUB1, $800, $100, $200, $300, $400, $500, $600, $700, $400, $500, $600, $700, $800 GotoW Main, SUB1 LookupW Main,ISR,SUB1, 1, 2, 3, 4095 call @SUB1:Entry ;global call to subroutine ; call SUB1 ;local call to subroutine VPS ;Virtual Peripherals ****************************** ;Time slice kernal goes here mov w, --VPSSlice snz mov w, #VPSCount mov VPSSlice, w GotoW UART, PWM UART ;Universal Asynchronous Receiver Transmitter ;(UART) Virtual Peripheral----------------------------- ;etc jmp @ISR:Out PWM ;Pulse Width Modulation Virtual Peripheral -------- ;etc jmp @ISR:Out ;SUBROUTINES ****************************************** ;with luck, the main program and VPS will push this ;into a new LowHalfPage. Subroutines can be rearranged ;manually to help the macros save memory. SUB1 Subroutine ;====================================== :Entry = SubEntryAddr nop ;do stuff jc @:Out :test djnc 10,@:test :Out --- James Newton 1-619-652-0593 mailto:jamesnewton@sxlist.com SX FAQ: http://www.sxlist.com -----Original Message----- From: pic microcontroller discussion list [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of James Newton Sent: Monday, November 06, 2000 15:15 To: PICLIST@MITVMA.MIT.EDU Subject: Re: [SX]: Memory layout? Importance: Low You sure? If you have an SX Key, try these out... I was playing around while I was waiting for responses: Subroutine MACRO GotoW Main, ISR, SUB1 LookupW Main, ISR, SUB1, 1, 2, 3 call @SUB1:Entry ;global call to subroutine call SUB1 ;local call to subroutine --- James Newton 1-619-652-0593 mailto:jamesnewton@sxlist.com SX FAQ: http://www.sxlist.com -----Original Message----- From: Michael Seiy [mailto:mikeseiy@home.com] Sent: Monday, November 06, 2000 14:49 To: sxtech@egroups.com Subject: Re: [sxtech] [SX]: Memory layout? Importance: Low I've always done it by hand on the PIC '5x series. Start with an ORG at 00h and put in as many jump tables as fit in the low half. Then do subroutines. Mike James Newton wrote: > Does anyone have some good ideas, doc's or samples that show more automatic > ways of getting the most out of the memory layout of the SX chips? Or the > PIC 16C5x chips? > > I'm looking at using macros to re-org and compile jump tables and other > things that use a relative or computed jumps or calls (including all > subroutine entries) in a reserved chunk of "first half of page" memory. > Seems like a hell of a waste. > > Ideally I'd like to find and document on the site the "best" layout of > memory in general (to support interrupts, debugging, subroutine placement > and calls, etc...) without having to shuffle things 500,000 times after each > code addition that over-runs the available "first half of page" space or > violates some other memory layout rule or .... > > BTW, if you haven't seen the exhaustive "how to do a comparison" table at > http://www.sxlist.com/../scenix/lib/flow/compcon_sx.htm > and the SXKey Structured Programming macros built from it at > http://www.sxlist.com/techref/default.asp?url=scenix/keymacs.src > you might want to check it out. This version is much more stable than the > last and it proves that you can really screw around with org in the SX Key > compiler... My testing hasn't found any bugs in a while so they may just > work for you! > > --- > James Newton 1-619-652-0593 > mailto:jamesnewton@sxlist.com > SX FAQ: http://www.sxlist.com > > Egroups help: http://www.egroups.com/info/help/main.html > > Parallax SX tech support: (916) 624-8333 > > -or- mailto:sxtech@parallaxinc.com Egroups help: http://www.egroups.com/info/help/main.html Parallax SX tech support: (916) 624-8333 -or- mailto:sxtech@parallaxinc.com -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! use mailto:listserv@mitvma.mit.edu?body=SET%20PICList%20DIGEST -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu