Dan Michaels wrote:
>Morgan Olsson  wrote:
>>
>>*Short description*
>>The error occours when using the polled mode, i.e activating the CS (Chip
>Select) to read the EOC flag (End Of Conversion) that LTC2400 then as
>response outputs in the SDO pin, then if it is ready we read out the=
 result,
>if it is not we deactivate CS and later test again.
>>
>>It then, very rarely, and not in all implemetations, happen, that the 32
>bit data comes in one bit too early.  Very funny, eh?
>............
>>
>
>Hello Morgan,
>
>I am not sure this pertains to what you are seeing, but the LTC1400/1404=
 chips
>have the following constraint on CS and Sclk timing:
>
>"If the time from CONV signal to CLK rising edge is less than
>t2, the digital output will be delayed by one clock cycle".

So to be safe, we need a delay of minimum of what t2 may be maximum.

>t2 is spec'ed at 80 nsec minimum - should not be a problem with a PIC, even
>running 20 Mhz.

But what is t2 maximum?
(Or maybe I did not understand your explanation?)

I have there tried a ridiculous 200 cycle delay @ 4MHz Xtal=3D 0,2=
 milliseconds - and experience no difference from using just a few cycles.=
=20


>There are also some constraints on how long the CS pulse can be - as
>related to accuracy of the final result.

On the LTC2400 it shold not matter, according to design.


Thanks for the quick input

Experiences of LTC2400 in polled mode, anybody?

Maybe the bug is gone in later produced chips?
Then the question is, from which date... (to make sure we do not buy the=
 elder bogus ones.)

Now, I have on my table two LTC2400 manufactured 1999 week 31, I=B4ll try to=
 find time to test them the coming week.

Regards
/Morgan

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