Olin wrote:
>> This is actually a serious inquiry. Any comments about having
>> dual-clock operation by putting 2 PICs exactly in parallel,
>> with each running off a different clock - say 20mhz vs 32khz ???
>
>I don't know how much a PIC draws if held in reset.  It's a static CMOS
>device, so probably very little, but you are still relying on unspeced
>values.


Yeah, that was one of my questions. There are powerdown values
given in the d/s, like 1.5uA, but am not sure it pertains to
/MCLR held continuously at 0.
===============


A cleaner way to switch between the PICs would be to control the
>power directly thru a series FET or something, or maybe have the "off"
>PIC go to sleep on its own.
>

A suspect there are several ways to deal with the on/off issue,
reset/sleep/wakeup interrupts/etc.
=============


>One problem with this whole concept is that each PIC will have its own local
>state.  You might be able to get around this by using a shared IIC ram or
>something.

With a reset hold idea, the PICs always go back to square 1 on powerup,
and with other solutions they, pickup where leftoff. These are issues
that would have to be dealt with during programming. Using I2C RAM/PROM
was one idea for dealing with this, if need be.
==============


I suppose this is all possible but it feels rather "messy".
>That usually means it's time to step back and look at the overall problem
>you are trying to solve again.
>

You are right. This is more of a solution looking for a problem. It
just seemed like such a strange unique idea, who knows what potential
it might have. And as someone else also pointed out, paralleling
PICs is rather ungainly - certainly with twin-40s, but it might be
more reasonable for twin-18s, say.

Actually a slightly different idea occurred to me out of this one.

Keep the low-power 32khz jobber running continuously to monitor
operation of the fast jobber, and as the major timer/controller/monitor
of the rest of the system, rather than the other way around. Use the
fast one more like a co-processor when you need the oomph. With this
arrangement, you might still have both uC's tied with a lot of pins
in parallel, I/O, A/D, etc. Alarm trips or A/D level thresholds,
little gun powers up the big gun.

An assymetrical scheme could use a small 8- or 18-pin device kind
of like a wart on the back of a big 28- or 40-pin guy, and "poaching"
on only the critical A/D or I/O pins. Hmmmmmmmm.

thanks,
- dan michaels
==============

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