> According to the manual for the 16F87x it is.  See "Table 8-2: Interaction
> of two CCP Modules" on page 57.  This may be different on other PICs - I
> haven't looked.  I also haven't personally played with this, but there is
> little reason to doubt such a direct assertion in the manual.

As i have described in my first message and different to that noted by the
manual and AN594, interaction of two CCP modules, one in capture and the
other in compare mode software interrupt only, works. I'm using the capture
for start bit detection, the compare for transmitting bit-per-bit. Tested
with 16C63, 16C66, 16F873 and various emulators.

The problem i've described, is capture together with compare, set/clear
output on match.
> If both events - CCP capture interrupt (start
> bit detection) and CCP compare interrupt (setup next transmit data) -
occur
> the same time, the CCP compare module changes the port pin, but the pin
goes
> into the previous state immediately, so there is a short peak only!!!
The compare fails if a capture event occurs the same time. Raising the
frequency from 4 to 20 MHz, the number of failures drops significant. I've
tried again capt2.asm from AN594 with some changes, and it works.
So i've played with my serial module and i've found the bug, i think so far.
In the capture routine, i do read timer1 to eleminate the latency time. For
simplicity, Timer1 is stopped, read and restart. If i don't stop timer1, the
module works. I will test this furthermore.

Hint: Don't stop timer1 if you use capture and compare with set/clear output
on match !!!

Frank
---------------------------
GSP Sprachtechnologie GmbH
Frank Wollenberg
HW-Entwicklung
Tel.:   +49 (0)30 769929-78
Fax:    +49 (0)30 769929-12
eMail:  f.wollenberg@gsp-berlin.de



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