Michael Rigby-Jones wrote:
>Ok, I have my analogue head on at the moment..(sort of)
>
>Has anyone used the above DAC?  It's a quad 12 bit device with SPI
>interface, just the job for a PIC containing product we are working on.
>However, it seems to have the worst clock breakthrough of any DAC I've ever
>seen, and the breakthrough occurs on all channels, not just the one being
>written to, (although that one is the worst).  I was convinced this was a
>grounding problem, but the PCB guys have done a good job AFAICT, the digital
>ground pin is routed to the PIC's ground pin, and then on to a digital
>ground plain.  The analogue ground pin connects to a separate analogue
>ground plane on the pcb.  The planes are joined at the power entry point via
>a small inductor.  The voltage references are well decoupled and appear to
>be very clean.
>

Hi Mike,

I haven't used this part but a couple of thoughts come to mind.

1. This may be a problem where you want to contact Maxim directly.

2. I think these sort of problems are pretty common on low pincount
   A/Ds, etc, that only have a single Gnd pin for both analog and
   digital, but as you say, this part has A & D separate gnds. I
   use an 8-pin SPI LT1404 A/D in one app, and decided having
   separate A & D gnd planes returned to a common point at power
   entry created large inductive loops. The trick in this case
   is "supposed" to be to connect the gnd planes beneath the chip,
   rather than at the P/S [but see below].

3. I assume your Vref pin is well filtered, but how about noise there?
   Do you have "both" small bypass and tantalum caps there?

4. Might try isolating the Vdd pin from the buss using a small R
   before your bypass cap. Also use a tantalum-bypass combo there.

5. How large actually is the passthru noise? The MAX525 d/s pg 6 does
   show a couple of mV of passthru with a 100 Khz clock. If your SPI
   is 5 Mhz or so, then noise will probably be larger.
===================

>The noise is really upsetting the operation of the circuit.  Software
>filtering has helped somewhat, but I'm sure that there must be something
>fundamentaly wrong for this much clock noise to be present.  My next hack
>was going to try to slew limit the SPI clock and data lines with a simple RC
>network.  Any ideas about this, or has anyone seen anything similar?
>

In the A/D ckt mentioned in item 2 above, I had to go this route to
reduce noise problems - use a 330ohm+27pF filter in the SPI lines
to reduce slewrates.

regards,
- Dan Michaels
Oricom Technologies
http://www.users.uswest.net/~oricom
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