> -----Original Message-----
> From: Olin Lathrop [SMTP:olin_piclist@COGNIVIS.COM]
> Sent: Friday, September 22, 2000 2:07 PM
> To:   PICLIST@MITVMA.MIT.EDU
> Subject:      Re: [PIC]: custom mpasm mnemonics
>
> > WAS:
> > > intr_off macro
> > >   if fam_16
> > >          bcf     intcon, gie
> > >     endif
> > >   if fam_17
> > >          bsf     cpusta, glintd
> > >     endif
> > >          endm
> >
> >
> > BETTER?:
> >  intr_off macro
> >    if fam_16
> >  foo:
> >           bcf     intcon, gie
> >           btfsc   intcon, gie
> >           goto    foo
> >      endif
> >    if fam_17
> >  bar:
> >           bsf     cpusta, glintd
> >           btfss   cpusta, glintd
> >           goto    bar
> >      endif
> >           endm
>
> I was the one who posted the original macro.  Is this true!?  Can an
> interrupt really happen immediately after the instruction that disables
> interrupts?  This seems hard to believe.  I've never seen any mention of
> this issue in the Microchip docs, and yes, I DO read the manual.  If this
> were really true I would expect at least a one of those gray boxes
> mentioning this issue.
>
> I just re-read the interrupt section of the 16F87x and 17C7xx data sheets
> and didn't see any mention of this issue.  Both mentioned a possible
> interrupt latency of up to 2 or 3 cycles from external conditions, but I
> am
> assuming the interrupt still can't take place if they are globally
> disabled.
> Someone from Microchip please confirm/deny this?
>
> By the way, if you are going to put labels in a macro like this, you
> really
> should declare them LOCAL.
>
Just had a quick look and I can not find any reference to this in the 16F87X
data sheets.  However, this was a known problem with the 16C6X and 16C7X
devices.  The datasheet says:
"If an interrupt occurs while the Global Interrupt Enable (GIE) bit isbeing
cleared, the GIE bit may unintentionaly be re-enabled by the users Interrupt
Service Routine (the RETFIE instruction)."
It then goes on to describe the work around which is as per the macro's
above.

Perhaps this has been fixed in later silicon?

Mike

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