I get the impression that holding MCLR low for longer than the worst case
startup time will synchronise PICs, assuming I read the explanation right
(long time ago) the osc runs and the startup timer counts all the time MCLR
is low, so I presume with an ext clock it could be done. MCLR might have to
be synchronised to the clock to prevent an occasional race condition that
would introduce 1 cycle uncertainty.

Otherwise I guess the generic (any deterministic micro) solution is to have
a loop that generates pulses until an 'OK' signal is returned by external
logic. The logic could suppress clock pulses to one PIC until they are in
step, then signal OK. A single edge might be enough?

Throws open the challenge: What's the least logic needed to do this?

Oliver.

----- Original Message -----
From: Dan Michaels <oricom@LYNX.SNI.NET>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Friday, September 22, 2000 8:32 PM
Subject: Re: [PIC]: Synchronizing two PICs


> Adam Davis wrote:
> >Ok, I understand this subject has been hashed before, but I've not seen
any
> >follow ups...  (see the 6/24/99 Thread "Dual pics, one xtal?")
> >
> >Can one reset two PICs such that they come up in the same state?  I'm
> interested
> >in real-world tests.
> >
> ..........
> >
>
>
> Interestingly, I have a project where I was wanting to do something
> similar in running up to 6 scenix SX28s - in cycle sync - off a common
> oscillator chip. So, anyone tried that [after first answering about
> PICs, of course]?
>
> --
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>

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