here's a handful of possibilities;
- chip designers often seperate core vcc/gnd and io vcc/gnd nets to limit noise in the core, and to
avoid io contentions affecting the core.
- more power pins improves io signal integrity due to closer return paths for signals
- how hard would a designer kick themselves if their beautiful design failed 1st silicon due to
power supply problems?

my vote for a change to the 877 pins would be to have a single pin, or even better just the clock
pins, used for ICD / ICP

Regards,
Simon

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